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tm
TE CH
T66H0004A
T66H0004A
80 output LCD Segment/Common Driver IC
DESCRIPTION
The T66H0004A is a LCD driver LSI which is fabricated by low power CMOS high voltage process technology. In segment driver mode, it can be interfaced in 1-bit serial or 4-bit parallel method by the controller. In common driver mode, dual type mode is applicable. And in segment mode application, the power down function reduces power consumption.
FEATURES
! ! ! ! ! ! ! ! Power supply voltage: +5V10% to +3V10% Supply voltage for display: 6 to 28V(VDD-VEE) 4 bit parallel/1 bit serial data processing (in segment mode) Single mode operation/dual mode operation (in common mode) Power down function (in segment mode) Applicable LCD duty:1/64 - 1/256 High voltage CMOS process Bare die , QFP or TQFP available
Ordering Information
Part No. T66H0004A-Q T66H0004A-T T66H0004A1S Pkg. Description QFP 100 pin TQFP 100 pin COG Refer to Pads List
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QFP
TE CH
T66H0004A
PACKAGE INFORMATION
100QFP PACKAGE
SC30
SC29
SC28
SC27
SC26
SC25
SC24
SC23
SC22
SC21
SC20
SC19
SC18
SC17
SC16
SC15
SC14
SC13
SC12
SC11
SC10
SC9
SC8
SC7
SC6
SC5
SC4
SC3
SC2 52
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
SC31 SC32 SC33 SC34 SC35 SC36 SC37 SC38 SC39 SC40 SC41 SC42 SC43 SC44 SC45 SC46 SC47 SC48 SC49 SC50
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
51
SC1
50 49 48 47 46 45 44 43 42 41
ELB CL1 AMS CL2 D1_SID D2_DL D3_DM D4_DR VSS SHL VDD D_OFF M CS V0 V12 V43 V5 VEE ERB
T66H0004A-Q
40 39 38 37 36 35 34 33 32 31
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29 SC79
SC51
SC52
SC53
SC54
SC55
SC56
SC57
SC58
SC59
SC60
SC61
SC62
SC63
SC64
SC65
SC66
SC67
SC68
SC69
SC70
SC71
SC72
SC73
SC74
SC75
SC76
SC77
SC78
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SC80
30
1
2
3
4
5
6
7
8
9
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TQFP
SC2
TE CH
T66H0004A
100TQFP PACKAGE
D1_SID
D2_DL
D3_DM
D4_DR
D_OFF
SC80
SC79 52
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
51
SC78
SC1
ELB
CL1
AMS
CL2
VSS
SHL
VDD
V12
V43
VEE
ERB
CS
V0
V5
M
SC3 SC4 SC5 SC6 SC7 SC8 SC9 SC10 SC11 SC12 SC13 SC14 SC15 SC16 SC17 SC18 SC19 SC20 SC21 SC22 SC23 SC24 SC25 SC26 SC27
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50 49 48 47 46 45 44 43 42 41 40 39
SC77 SC76 SC75 SC74 SC73 SC72 SC71 SC70 SC69 SC68 SC67 SC66 SC65 SC64 SC63 SC62 SC61 SC60 SC59 SC58 SC57 SC56 SC55 SC54 SC53
T66H0004A-T
38 37 36 35 34 33 32 31 30 29 28 27 26
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 SC51
SC28
SC29
SC30
SC31
SC32
SC33
SC34
SC35
SC36
SC37
SC38
SC39
SC40
SC41
SC42
SC43
SC44
SC45
SC46
SC47
SC48
SC49
SC50
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SC52
25
1
2
3
4
5
6
7
8
9
tm
TE CH
T66H0004A
BLOCK DIAGRAM
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Name
TE CH
T66H0004A
BLOCK DESCRIPTION
Function COM/SEG Generates latch clock (LCK),shift clock(SCK) and control clock timing according to the input of CL1,CL2 and control inputs(CS,AMS). In COM/SEG common driver application mode, this block generates the shift clock (LCK) for the common data Bi-directional shift register. Determines the direction of segment data shift, and input data of each Bi-directional shift register. In 4-bit segment data parallel transfer mode, SEG data is shifted by 4-bit unit. In common driver application mode, data is transferred to the common data shift register directly, which disables this block. Controls the clock enable state of the current driver according to the input value of enable pin (ELB or ERB). If enable input value is "Low", every clock of the current driver is enabled and the clock control block SEG works. But if enable input is "High", current driver is disabled and the input data value has no effect on the output level. So power consumption can be lowered. Controls the output voltage level according to the input control pin (M COM/SEG and DISPOFFB) (refer to PIN DESCRIPTION). Stores output data value by shifting the input values. In 1-bit serial interface mode application, all 80 shift clocks (SCK) are needed to store SEG all the display data. But in 4-bit parallel transfer mode application, only 20 clocks are needed. In common driver application mode, this block does not work. In segment driver application mode, the data from the 20x4-bit segment data shift register are latched for segment driver output. In single-type common driver application, 1-bit input data (from DL or DR pin) is COM/SEG shifted and latched by the direction according to the SHL signal input. In dual-type common application mode, 80-bit registers are divided by two blocks and controlled independently (refer to NOTE 3). Voltage level shifter block for high voltage part. The inputs of this block SEG are of logical voltage level and the outputs of this block are at high voltage level value. These values are output to the driver. Selects the output voltage level according to M and latched data value. If the data value is "High" the driver output is at selected voltage level (V0 or V5), and in the reverse case the driver output value is at the SEG non-selected level (V12 or V43). In segment driver application mode, non-selected output value is V2 or V3. And when in common driver application, this value becomes V1 or V4.
Clock control
Data latch control
Power down function
Output level selector 20x4-bit segment data Bi-directional shift register 80-bit data latch/common data Bi-directional shift register 80-bit level shifter
80-bit 4-level driver
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Pin VDD Vss VEE V0,V12, V43,V5
TE CH
T66H0004A
PIN DESCRIPTION
I/O Name Power supply LCD driver output voltage level LCD driver output Function Interface Logical "High" input port(+5V10%,+3V10%) Power 0V(GND) Logical "Low" for high voltage part Bias supply voltage input to drive the LCD. Bias voltage divided by the resistance is usually used as a Power supply voltage source (refer to NOTE 2). Display data output pin which corresponds to the respective latch contents. One of V0, V12, V34 and V5 LCD is selected as a display driving voltage source according to the combination of the latch data level and M signal (refer to NOTE 1). Clock pulse input for the bi-directional shift register. - In segment driver application mode, the data is shifted to 20x4-bit segment data shift. The clock pulse, which was input when the enable bit (ELB/ERB) is in not active condition, is invalid. Controller - In common driver application mode, the data is shifted to 80-bit common data bi-directional shift register by the CL1 clock. Hence, this clock pin is not used (Open or connect this pin to VDD). Alternate signal input pin for LCD driving. Normal frame inversion signal is input in to this pin. Controller
I
SC1-SC80
O
CL2
I
Data shift clock
M
I
AC signal for LCD driver output
CL1
I
DISPOFFB
I
CS
I
AMS
I
- In segment driver application mode, this signal is used for latching the shift register contents at the falling edge of this clock pulse. Data latch CL1 pulse "High" level initializes power-down Controller clock function block. - In common driver application mode, CL1 is used as a shifting clock of common output data. Control input pin to fix the driver output (SC1-SC80) Display OFF to V0 level, during "Low" value input. LCD becomes Controller control non-selected by V0 level output from every output of segment drivers and every output of common drivers. When CS = "Low", T66H0004A is used as an 80-bit COM/SEG segment driver. VDD/VSS mode control When CS = "High", T66H0004A is set to an 80-bit common driver. According to the input value of the AMS and the CS pin, application mode of T66H0004A is differs as shown below. CS AMS Application mode 0 4-bit parallel interface mode SEG Application 0 VDD/VSS mode select 0 1 1-bit serial interface mode 1 0 Single type application mode COM
D1_SID, D2_DL,
I/O
1 1 Dual type application mode Display data - In segment driver application mode, these pins are Controller input/serial used as 4-bit data input pin (when 4-bit parallel
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D3_DM, D4_DR
TE CH
T66H0004A
SHL
ELB,ERB
input data/left, interface mode: AMS = "Low"), or D1_SID is used as right data serial data input pin and other pins are not used input output (connect these to VDD) (when 1-bit serial interface mode: AMS = "High"). - In common driver application mode, the data is shifted from D2_DL(D4_DR) to D4_DR (D2_DL),when in single type interface mode (AMS = "Low"). In dual-type application case, the data are shifted from D2_DL and D3_DM (D4_DR and D3_DM) to D4_DR(D2_DL). In each case the direction of the data shift and the connection of data pins are determined by SHL input (refer to NOTE3, NOTE4). When SHL = "Low", data is shifted from left to right. Shift direction Input When SHL = "High", the direction is reversed.(refer to VDD/VSS control NOTE3) - In segment driver application mode, the internal operation is enabled only when enable input (ELB or ERB) is "Low" (power down function). When several drivers are serially connected, the enable state of each driver is shifted according to the SHL input. Connect these pins as below. Enable data SHL Segment Driver I/O input/output ELB ERB L Output(open) Input(VSS) H Input(VSS) Output(open) - In common driver application mode, power down function is not used. Open these pins.
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M L L H H X
TE CH
T66H0004A
NOTE 1. Output Level Control Output level(SC1-SC80) Latched data DISPOFFB SEG Mode COM Mode L H V12(V2) V12(V1) H H V0 V5 L H V43(V3) V43(V4) H H V5 V0 X L V0 V0
NOTE 2. LCD Driving Voltage Application Circuit (1) Segment driver application(CS = "Low")
(2) Common driver application(CS = "High")
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TE CH
T66H0004A
NOTE 3. Data Shift Direction according to Control Signals (1) When CS = "Low"(Segment driver application) AMS SHL Application Data Direction Input Pin mode
ssss cccc 1234 DDDD 1234 s c 7 3 s c 7 4 s c 7 5 s c 7 6 s c 7 7 s c 7 8 s c 7 9 s c 8 0
L
D1 D2 data D3 D4
DDDDDDDD 12341234 Shift Direction
last data
first
L
4-Bit Parallel Data Transfer Mode(SEG)
ssss cccc 1234 DDDD 4321
s c 7 3
s c 7 4
s c 7 5
s c 7 6
s c 7 7
s c 7 8
s c 7 9
s c 8 0
D1_SID, D2_DL, D3_DM, D4_DR
H
DDDDDDDD 43214321 Shift Direction D1 D2 D3 D4
first last data
data
L 1-Bit Serial Data Transfer Mode (SEG) H
ssss cccc 1234
s c 7 3
s c 7 4
s c 7 5
s c 7 6
s c 7 7
s c 7 8
s c 7 9
s c 8 0
Shift Direction
H
last data (D1_SID) data ssss cccc 1234 s c 7 3 s c 7 4 s c 7 5 s c 7 6 s c 7 7 s c 7 8 s c 7 9 s c 8 0
first
D1_SID
Shift Direction first data last data
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TE CH
T66H0004A
(2) When CS = "High"(common driver application) AMS SHL Application Data Direction mode
Shift Direction SSS CCC 123 S C 3 8 S C 3 9 S C 4 0 S C 4 1 S C 4 2 S C 4 3 S C 7 8 S C 7 9 S C 8 0
Input Pin
L
D2_DL
L
Single-type Application Mode (COM) H
Input Data (D2 DL)
Output Data (D4_DR)
Shift Direction SSS CCC 123 S C 3 8 S C 3 9 S C 4 0 S C 4 1 S C 4 2 S C 4 3 S C 7 8 S C 7 9 S C 8 0
D4_DR
Output Data (D2_DL)
Input Data (D4 DR)
Shift Direction SSS CCC 123 S C 3 8 S C 3 9 S C 4 0 S C 4 1 S C 4 2 S C 4 3 S C 7 8 S C 7 9 S C 8 0
L
D2_DL, D3_DM
H
Dual-type Application Mode (COM) H
Input Data 1 (D2_DL)
Input Data 2 (D3_DM)
Output Data (D4_DR)
Shift Direction SSS CCC 123 S C 3 8 S C 3 9 S C 4 0 S C 4 1 S C 4 2 S C 4 3 S C 7 8 S C 7 9 S C 8 0
D4_DR, D3_DM
Output Data (D2_DL)
Input Data 2 (D3_DM)
Input Data 1 (D4_DR)
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TE CH
T66H0004A
NOTE 4. Usage of Data Pins COM/SEG Application mode SHL Data interface pin (CS pin) (AMS pin) D1_SID D2_DL D3_DM
4-bit parallel interface mode(AMS = "Low") SEG (CS = "Low") 1-bit serial interface mode (AMS = "High") Single-type application mode( AMS = "Low") COM (CS = "High") Dual-type application mode (AMS = "high") X X L H L H D1(input) SID(input) Open Open D2(input2) D3(input3)
D4_DR
D4(input4)
Connect to VDD DL(input) DR(output) Open DL(output) DR(input) DL(input1) DM(input2) DR(output2) DL(output2) DM(input2) DR(input1)
MAXIMUM ABSOLUTE LIMIT Value -0.3 to +7.0 0 to +30 -0.3 to Input voltage Vin VDD+0.3 Operating temperature Topr -30 to +85 Storage temperature Tstg -55 to +150 *NOTE: Voltage greater than above may do damage to the circuit. Characteristic Power supply voltage Driver supply voltage Symbol VDD Vlcd Unit V
*
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TE CH
T66H0004A
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
(1) Segment Driver Application
(Vss = 0V, Ta=-30 to +85 C) Characteristic Operating Voltage 1 Input voltage (1) Output voltage (2) Input leakage current 1 (1) Input leakage current 2 (3) On resistance (4) Symbol VDD VLCD VIH Test Condition VIN = VDD -VEE Min. 2.7 6 0.8VDD Typ. Max. 5.5 28 VDD Unit
0
V
VI L
VOH VOL IIL1 IIL2 RON ISTBY Supply current (5)
IOH = -0.4mA IOL = 0.4mA VIN = VDD to Vss VIN = VDD to VEE ION = 100uA FCL1 =32 KHz M=Vss Vss pin VDD= 5V
0
VDD-0.4 -10 -25 -
2 -
0.2 VDD
0.4 10 25 4 50 5 2 500 mA uA V
uA
KOhm
uA
IDD IEE
FCL1 = 32KHz FM = 80Hz
VDD = 3V VDD =5V
NOTES: 1. Applied to Cl1,CL2,ELB,ERB,D1_SID-D4_DR,SHL,DISPOFFB,M,CS,AMS pin 2. ELB,ERB pin 3. V0,V12,V43,V5 pin 4. VLCD = VDD -VEE, V0=VDD =5V, V5=VEE=-23V V12 = VDD -2/n(VLCD), V43= VEE +2/n(VLCD), n=17(1/256 duty,1/17 bias) 5. V0= VDD, V12=1.71V(VDD =5V) or -0.06V(VDD =3V) V43=-19.71V(VDD =5V) or -19.94V(VDD =3V), V5=VEE=-23V, no-load condition (1/256 duty,1/17 bias) 4-bit parallel interface mode. Istby: VDD =5V, CL2=Vss, SHL=Vss, DISPOFFB= VDD, M = Vss, display data pattern=0000 IDD: VDD =3V, fCL2=4MHz, display data pattern=0101 VDD = 5V, fCL2 fCL2=5.12MHz, display data pattern=0101
IEE: VDD=5V, fCL2=5.12MHz, display data pattern=0101, VEE pin
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TE CH
T66H0004A
ELECTRICAL CHARACTERISTICS
(2) Common Driver Application
(Vss = 0V, Ta=-30 to +85 C) Characteristic Operating Voltage Input voltage (1) Output voltage (3) Input leakage current 1 (1) Input leakage current 2 (2) Input leakage current 3 (4) On resistance (5) Supply current(6) Symbol VDD VLCD VIH Test Condition VIN = VDD -VEE Min. 2.7 6 0.8 VDD Typ. Max. 5.5 28 VDD Unit
0
V
VIL
-
0
-
0.2 VDD
0.4 10 -250 25 4 50 200 120 150 V
VOH IOH = -0.4mA VDD -0.4 IOL = 0.4mA VOL IIL1 VIN = VDD to Vss -10 IIL2 VIN=0, VDD =5V(PULL UP) -50 -125 IIL3 VIN = VDD to VEE -25 RON ION = 100uA 2 ISTBY FCL1=32KHz Vss pin VDD =5V IDD FCL1=32KHz VDD =3V FM=80Hz VDD =5V IEE
uA
KOhm
uA
NOTES: 1. Applied to CL1, D2_DL (SHL=LOW), D4_DR (SHL=HIGH), SHL, DISPOFFB, M, CS, AMS pin. 2. Pull-up input pins: CL2, D1_SID, D3_DM (AMS=HIGH), ELB (SHL=LOW), ERB (SHL= HIGH). 3. D2_DL (SHL = HIGH), D4_DR (SHL = LOW) pin. 4. V0, V12, V43, V5 pin 5. VLCD = VDD -VEE, V0= VDD =5V,V5=VEE=-23V V12 = VDD -1/n(VLCD), V43= VEE +1/n(VLCD), n=17(1/256 duty, 1/17 bias) 6. V0= VDD, V12=3.35V(VDD =5V) or 1.47V(VDD =3V), V43=-21.35V(VDD =5V) or -21.47V(VDD =3V), V5= VEE =-23V, no-load condition (1/256 duty, 1/17 bias)Single-type mode operation: AMS = Vss, SHL = Vss, DISPOFFB = VDD D1_SID=D3_DM=VDD, D4_DR=OPEN, ELB+ERB+OPEN, ISTBY: VDD =5V, M=Vss, D2_DL=Vss IDD: fM=80Hz, D2_DL= VDD VDD =3V, display data pattern=10000000...,01000000...,00100000...,00010000...,... VDD =5V.displat data pattern=10000000...,01000000...,00100000...,00010000...,... IEE: fM=80Hz,D2_DL= VDD VDD =5V, current through VEE pin, display data pattern=100000000...,01000000...,00100000...,00010000...,...
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TE CH
T66H0004A
AC CHARACTERRISTICS
(1) Segment Driver Application
(Vss = 0V, Ta=-30 to +85 C) (1) VDD=5V10% Characteristic Clock cycle time Clock pulse width Clock rise/fall time Data set-up time Data hold time Clock set-up time Clock hold time Propagation delay time ELB,ERB set-up time DISPOFFB low pulse width DISPOFFB clear time M-OUT propagation delay time CL1-OUT propagation delay time DISPOFFB-OUT propagation delay time Latch pulse rise to Shift clock rise time Symbol Test Condition tcy twck tR/tF tDS tDH tcs tch tphl tpsu tWDL tcd tpd1 tpd2 Duty=50% ELB Output ERB Output ELB Input ERB Input Min. 125 45 30 30 80 80 30 30 1.2 100 Typ. 30 60 60 1.0 1.0 (2) VDD=3V10% Unit 250 95 65 65 120 120 65 65 1.2 100 1.2 1.2 30 125 125 us ns
0
Max. Min. Typ. Max.
ns
CL=15pF
us
tpd3 tLS
80
-
1.0 -
120
-
1.2 ns
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TE CH
T66H0004A
AC CHARACTERISTICS
(2) Common Driver Application
(Vss = 0V, Ta=-30 to +85 C) (1) VDD=5V10% Characteristic Clock cycle time Clock pulse width Clock rise/fall time Data set-up time Data hold time DISPOFFB low pulse width DISPOFFB clear time Output delay time M-OUT propagation delay time CL1-OUT propagation delay time DISPOFFB-OUT propagation delay time Symbol Test Condition tcy twck tR/tF tDS tDH twdl tcd tdl tpd1 tpd2 CL=15pF Duty=50% Min. 250 45 30 30 1.2 100 Typ. 50 200 1.0 1.0 (2) VDD=3V10% Unit 500 95 65 65 1.2 100 250 1.2 1.2 50 0
Max. Min. Typ. Max.
ns
us ns
us
tpd3
-
-
1.0
-
-
1.2
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TE CH
T66H0004A
AC CHARACTERISTICS
(3) Segment Driver Application Timing
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TE CH
T66H0004A
AC CHARACTERISTICS
(4) Common Driver Application Timing
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L H
TE CH
T66H0004A
POWER DOWN FUNCTION
In the case of cascade connection of segment mode drivers,T66H0004A has a "power down function" In order to reduce the power consumption.
SHL Enable input Enable output ERB ELB ELB ERB Current driver status The other drivers status While ERB = "Low", current Disabled driver is enabled. While ELB = "Low", current Disabled driver is enabled
* In the case of common driver application, power down function dose not work.
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!
TE CH
T66H0004A
OPERATION TIMING DIAGRAM
(1) 4-bit Parallel Mode Interface Segment Driver
When SHL = "High"
!
When SHL = "Low"
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!
TE CH
T66H0004A
(2) 1-bit Serial Mode Interface Segment Driver
When SHL = High"
!
When SHL = "Low"
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TE CH
T66H0004A
(3) Single-type Interface Mode Common Driver ! When SHL = "Low"
!
When SHL = "High"
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TE CH
T66H0004A
(4) DUAL-type Interface Mode Common Driver ! When SHL = "Low"
!
When SHL = "High"
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TE CH
T66H0004A
(5) Common/Segment driver Timing(1/200 DUTY)
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TE CH
T66H0004A
APPLICATION INFORMATION
1-bit Serial Interface Mode (80 output Segment Driver) (a)Lower View(SHL = L , AMS = H )
(b)Upper View (SHL = H, AMS = H)
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TE CH
T66H0004A
4-bit Parallel Interface Mode (80 output Segment Driver) (a) Lower View(SHL = L , AMS = L)
(b) Upper View (SHL = H , AMS = L)
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TE CH
T66H0004A
Single-type Interface Mode (80 output Common Driver)
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TE CH
T66H0004A
Dual-type Interface Mode (40 output Common Driver)
NOTE: Using this application mode (dual-type common mode), the duty ratio can be reduced to half.
In case, 1/200 duty can be used to drive the 400 common LCD panel.
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TE CH
T66H0004A
APPLICATION CIRCUIT EXAMPLE
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TE CH
(Unit: mm)
T66H0004A
PACKAGE DIMENSION
100 pin TQFP
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TE CH
T66H0004A
100 pin QFP
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TE CH
T66H0004A
Pad List(For T66H0004A1S use)
Pad No. Pin Name 1 Y51 2 Y52 3 Y53 4 Y54 5 Y55 6 Y56 7 Y57 8 Y58 9 Y59 10 Y60 11 Y61 12 Y62 13 Y63 14 Y64 15 Y65 16 Y66 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Y67 Y68 Y69 Y70 Y71 Y72 Y73 Y74 Y75 Y76 Y77 Y78 Y79 Y80 X -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 Y 1473.25 1373.25 1273.25 1173.25 1073.25 973.25 873.25 773.25 673.25 573.25 473.25 373.25 273.25 173.25 73.25 -26.75 Pad No. Pin Name 36 VOP:P 37 CS 38 M 39 DISSPO 40 VDD 41 SHL 42 VSS 43 D4_DR 44 D3_DM 45 D2_DL 46 D1_SID 47 CL2 48 AMS 49 CL1 50 ELB 51 Y1 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 X -449.75 -349.75 -249.75 -149.75 -49.75 50.25 150.25 250.25 350.25 450.25 550.25 650.25 750.25 850.25 950.25 1127.7 1127.7 1127.7 1127.7 1127.7 1127.7 1127.7 1127.7 1127.7 1127.7 1127.7 Y -1534.4 -1534.4 -1534.4 -1534.4 -1534.4 -1534.4 -1534.4 -1534.4 -1534.4 -1534.4 -1534.4 -1534.4 -1534.4 -1534.4 -1534.4 -1426.7 5 -1326.7 5 -1226.7 5 -1126.7 5 -1026.7 5 -926.75 -826.75 -726.75 -626.75 -526.75 -426.75
-1127.2 -126.75 -1127.2 -226.75 -1127.2 -326.75 -1127.2 -426.75 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -1127.2 -526.75 -626.75 -726.75 -826.75 -926.75 -1026.7 5 -1126.7 5 -1226.7 5 -1326.7 5 -1426.7 5 -1534.4 -1534.4
1127.7 -326.75 1127.7 -226.75 1127.7 -126.75 1127.7 -26.75 1127.7 73.25 1127.7 173.25
-949.75 ERB VEEP:G -849.75
TM Technology Inc. reserves the right P. 31 to change products or specifications without notice.
Publication Date: MAR. 2004 Revision:A
tm
33 34 35
TE CH
V5P V43P V12P -749.75 -1534.4 -649.75 -1534.4 -549.75 -1534.4 X 1127.7 1127.7 1127.7 1127.7 1127.7 1127.7 1127.7 1127.7 1127.7 1127.7 950.25 850.25 Y 573.25 673.25 773.25 873.25 973.25 1073.25 1173.25 1273.25 1373.25 1473.25 1534.4 1534.4 68 69 70 88 89 90 91 92 93 94 95 96 97 98 99 100 Y18 Y19 Y20 Y38 Y39 Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50
T66H0004A
1127.7 273.25 1127.7 373.25 1127.7 473.25 250.25 150.25 50.25 -49.75 -149.75 -249.75 -349.75 -449.75 -549.75 -649.75 -749.75 -849.75 -949.75 1534.4 1534.4 1534.4 1534.4 1534.4 1534.4 1534.4 1534.4 1534.4 1534.4 1534.4 1534.4 1534.4
Pad No. Pin Name 71 Y21 72 Y22 73 Y23 74 Y24 75 Y25 76 Y26 77 Y27 78 Y28 79 Y29 80 Y30 81 Y31 82 Y32 83 Y33 84 85 86 87 Y34 Y35 Y36 Y37
750.25 1534.4 650.25 1534.4 550.25 1534.4 450.25 1534.4 350.25 1534.4
CHIP SIZE ==> ( 2349.4,3163.8 )
Y50 Y51
Y31 Y30
T66H0004A1S
ELB CL1 AMS CL2 D1_SID D2_DL D3_DM D4_DR VSS SHL VDD DISPOFF M CS V0 V12 V43 V5 VEE ERB
Y80
Y1
TM Technology Inc. reserves the right P. 32 to change products or specifications without notice.
Publication Date: MAR. 2004 Revision:A

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